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TC9WMC1FK/FU,TC9WMC2FK/FU
TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic
TC9WMC1FK,TC9WMC1FU,TC9WMC2FK,TC9WMC2FU
TC9WMC1FK/FU: 1024-Bit (64 x 16-Bit) 3-Wire Serial EEPROM TC9WMC2FK/FU: 2048-Bit (128 x 16-Bit) 3-Wire Serial EEPROM
The TC9WMC1 and TC9WMC2 are electrically erasable/programmable three-wire serial nonvolatile memories (EEPROMs).
TC9WMC1FK,TC9WMC2FK
Features
* * * * * Three-wire serial interface (MICROWIRE) Automatic address incrementing during read operation Hardware and software data protection
READY/ BUSY signal during programming
US8 TC9WMC1FU,TC9WMC2FU
Single power supply and low power consumption Read: VCC = 1.8 to 3.6 V Write: VCC = 2.3 to 3.6 V Wide operating temperature range (-40 to 85C)
*
SM8
Weight: SSOP8-P-0.50A: 0.01 g (typ.) SSOP8-P-0.65: 0.02 g (typ.)
Product Marking
US8 Part number C1 or C2
Pin Assignment (top view)
CS 8 SK 7 DI 6 DO 5
9WM xx
Pin 1 index
US8
1 SM8 Part number
2
3
4
VCC NC TEST GND VCC NC TEST GND 8 7 6 5
WMxx
C1 or C2 LotNo. Pin 1 index
SM8
1 CS
2 SK
3 DI
4 DO
1
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
Block Diagram
Test input TEST
Chip select: CS Clock input: SK
Timing generator
Control circuit
Power supply (booster circuit)
VCC power supply
Command register Data input: DI Input/output circuit Address Address register decoder Memory cell GND
Data output: DO
Data register
Pin Function
Pin Name Input/Output Function Chip select input The device receives an instruction set when this pin is driven High. This pin must be driven Low before execution of an instruction. Serial clock input Data is latched on the rising edge of SK. Data is transferred on the rising edge of SK. This pin is valid when CS is driven High. Serial data input (start bit, op code, address and data) Serial data output Test mode input (internal pull-down resistor) Normally kept open. (Can be connected to GND.) No connection (not connected internally) 1.8 to 3.6 V (for reading) 2.3 to 3.6 V (for writing) 0 V (GND)
CS
Input
SK DI DO TEST NC VCC GND
Input Input Output Input Power supply
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TC9WMC1FK/FU,TC9WMC2FK/FU
1. Instruction Set
Instruction READ (Read) WRITE (Write) ERASE (Erase) WRAL (Write All) ERAL (Erase All) EWEN (Program Enable) EWDS (Program Disable) Start Bit 1 1 1 1 1 1 1 Op Code 10 01 11 00 00 00 00 Address TC9WMC1 A5 to A0 A5 to A0 A5 to A0 01xxxx 10xxxx 11xxxx 00xxxx TC9WMC2 xA6 to A0 xA6 to A0 xA6 to A0 01xxxxxx 10xxxxxx 11xxxxxx 00xxxxxx D15 to D0 outputs D15 to D0 inputs D15 to D0 inputs Data
x: Don't care
2. Functional Description
All instructions are executed when the DI input is received on the rising edge of SK after the CS input is driven High. An instruction starts with a start bit followed by an op code, address and data bits. The instruction transfer is completed when the CS input is driven Low. The CS must be driven Low during the tCS cycle period between instruction transfers. When the CS is Low, the device is in standby mode. The SK and DI inputs are disabled and the device does not respond to any instructions. (1) Start bit After the CS is driven High, a High on the DI input on the rising edge of SK indicates a start bit. A start bit is not identified if the DI is driven Low even after the CS is driven High and the SK pulse is applied. Refer to (2) Dummy cycle in Section 3, Notes on Use. Read operation (READ) The Read instruction reads data at specified addresses. After the CS is driven High, a start bit, READ instruction and address are transferred to the device. After the least significant bit of address (A0) is received, the DO output changes from high impedance to logic Low on the 9th rising edge of SK. On the 10th rising edge of SK, the 16 bits of data appear on the DO output. Sequential read After the 16 bits of data are driven onto the DO output, the device will automatically increment the internal address counter and clock out data in the next memory location as long as the CS is held High and the SK pulse is applied. In this way, data in all the memory locations can be read in sequence. After the data in the last memory address is read, the address counter rolls over to the first memory address.
(2)
(2.1)
CS 39 40 DI 42
1 2 3 4 5 6 7 8 9 10 11 12 SK
23 24 25 26 27 28
D
DI
1 1 0 A5 A4 A3 A2 A1 A0
DO
Hi-Z
D15 D14 D13
D2 D1 D0 D15 D14 D13
D2 D1 D0 D15
Hi-Z
Figure 1. Read Timing Diagram (TC9WMC1) 3 2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 SK
26 27 28 29
41 42 43 44
DI
1 1 0 x A6 A5 A4 A3 A2 A1 A0
DO
Hi-Z
D15 D14 D13
D1 D0 D15 D14
D2 D1 D0 D15
Hi-Z
Figure 2. Read Timing Diagram (TC9WMC2)
(3)
Write operation (WRITE, ERASE, WRAL, ERAL) The write operation has four modes: Write (WRITE), Erase (ERASE), Write All (WRAL) and Erase All (ERAL). The write operation is triggered when the CS is driven Low after the SK pulse is applied. The SK and DI inputs are disabled during the write operation, so no attempt should be made to transfer instructions at this time. If 16-bit or longer data is transferred to the device, the first 16 bits of data are valid and the remaining bits are ignored. The DO output must be held High or in the high-impedance state when a write instruction is received. A write operation is enabled in program enable mode. Verify operation A write operation in all write modes is completed within 10 ms (write cycle tPW), but the typical write cycle is shorter (5 ms). If the completion of the write operation is known, the internal write cycle can be minimized. To accomplish this, a verify operation is performed. (a) Operational description When the CS is brought High following the initiation of a write operation (CS = Low), the write operation status can be seen by monitoring the DO pin. This is called a verify operation and the period during which the CS is held High following the initiation of a write operation is called a verify operation cycle. * DO pin = Low: A write operation is in progress. (busy) * DO pin = High: A write operation has been completed. (ready) After the write operation is completed, and if a start bit is not identified, the DO pin goes to the high-impedance state if the CS is Low. If the CS is Low, the DO pin is driven High. When the write operation is in progress (busy), the SK and DI inputs are disabled. Once the write operation has been completed and a start bit is received, the verify operation is stopped. (b) Two operation methods There are two ways to perform a verify operation. One way is to monitor the DO output successively with the CS driven High until the DO output status changes. The other way is to monitor the DO output and, if no change is evident, the verify operation is stopped (CS = Low). The verify operation is then restarted by the CS being pulled High. In this way, when the DO output is not being monitored, the CPU is free for other operations, thus allowing more efficient design of electronic systems.
(3.1)
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(3.2) Write (WRITE) The Write instruction contains the 16 bits of data to be written into the specified memory location. After the CS is driven High, a start bit is transferred followed by the WRITE instruction, address and 16 bits of data. After the least significant bit (D0) of data is received on the rising edge of SK, a write operation is triggered by the CS being pulled Low. It is not necessary to set every bit in the memory array to "1" before writing data.
CS
Verify
1 2 3 4 5 6 7 8 9 10 SK
25
DI
1 0 1 A5 A4 A3 A2 A1 A0 D15
D0
DO
Busy Hi-Z tPW
Ready
Hi-Z
Figure 3. Write Timing Diagram (TC9WMC1)
CS
Verify
1 2 3 4 5 6 7 8 9 10 11 12 SK
27
DI
1 0 1 x A6 A5 A4 A3 A2 A1 A0 D15
D0
DO
Busy Hi-Z tPW
Ready
Hi-Z
Figure 4. Write Timing Diagram (TC9WMC2)
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TC9WMC1FK/FU,TC9WMC2FK/FU
(3.3) Erase (ERASE) The Erase instruction writes all bits in the specified memory location to 1. After the CS is driven High, a start bit is transferred followed by the ERASE instruction and address. In this mode, data does not need to be transferred. After the least significant bit (A0) of the address is received on the falling edge of SK, an erase operation is triggered by the CS being pulled Low.
CS
Verify
123456789 SK
DI
1 1 1 A5 A4 A3 A2 A1 A0
DO
Busy Hi-Z tPW
Ready
Hi-Z
Figure 5. Erase Timing Diagram (TC9WMC1)
CS
Verify
1 2 3 4 5 6 7 8 9 10 11 SK
DI
1 1 1 x A6 A5 A4 A3 A2 A1 A0
DO
Busy Hi-Z tPW
Ready
Hi-Z
Figure 6. Erase Timing Diagram (TC9WMC2)
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TC9WMC1FK/FU,TC9WMC2FK/FU
(3.4) Write All (WRAL) The Write All instruction writes all memory locations with data patterns specified in the instruction. The data is 16 bits long. After the CS is driven High, a start bit is transferred followed by the WRAL instruction, any addresses and 16 bits of data. After the least significant bit (D0) of data is received on the falling edge of SK, a write operation is triggered by the CS being pulled Low. It is not necessary to set every bit in the memory array to "1" before writing data.
CS
Verify
1 2 3 4 5 6 7 8 9 10 SK
25
DI
10001x
x
x
x
D15
D0
DO
Busy Hi-Z tPW
Ready
Hi-Z
Figure 7. Write Timing Diagram (TC9WMC1)
CS
Verify
1 2 3 4 5 6 7 8 9 10 11 12 SK
27
DI
10001x
x
x
x
x
x
D15
D0
DO
Busy Hi-Z tPW
Ready
Hi-Z
Figure 8. Write Timing Diagram (TC9WMC2)
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TC9WMC1FK/FU,TC9WMC2FK/FU
(3.5) Erase All (ERASE) The Erase All instruction writes every bit in the memory array to 1. After the CS is driven High, a start bit is transferred followed by the ERAL instruction and any addresses. In this mode, data does not need to be transferred. After the least significant bit (A0) of the address is received on the falling edge of SK, an erase operation is triggered by the CS being pulled Low.
CS
Verify
123456789 SK
DI
10010x
x
x
x
DO
Hi-Z
tPW
Busy
Ready
Hi-Z
Figure 9. Erase Timing Diagram (TC9WMC1)
CS
Verify
1 2 3 4 5 6 7 8 9 10 11 SK
DI
10010x
x
x
x
x
x
DO
Hi-Z
tPW
Busy
Ready
Hi-Z
Figure 10. Erase Timing Diagram (TC9WMC2)
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TC9WMC1FK/FU,TC9WMC2FK/FU
(3.6) Write Enable (EWEN)/Write Disable (EWDS) The EWEN instruction enables a write operation. In program enable mode, a writing operation is enabled. The EWDS instruction disables a write operation. In program disable mode, a writing operation is disabled. After power on, the device is in EWDS mode. The EWEN instruction must be executed before any write instructions can be carried out. After the CS is driven High, a start bit is transferred followed by the EWEN/EWDS instruction and any addresses. The mode is enabled on the rising edge of SK after the least significant bit (A0) of the address is received.
CS
CS
123456789 SK SK
123456789
DI
10011x
x
x
x
DI
10000x
x
x
x
Write enabled
Write disabled
Figure 11. Write Enable/Disable Timing Diagram (TC9WMC1)
CS
CS
1 2 3 4 5 6 7 8 9 10 11 SK SK
1 2 3 4 5 6 7 8 9 10 11
DI
10011x
x
x
x
x
x
DI
10000x
x
x
x
x
x
Write enabled
Write disabled
Figure 12. Write Enable/Disable Timing Diagram (TC9WMC2)
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TC9WMC1FK/FU,TC9WMC2FK/FU
3. Notes on Use
(1) Powering up the device This device contains a power-on clear circuit, which initializes the internal circuit of the device when the power is turned on. If initialization fails, the chip may malfunction. When powering up the device, observe the following precautions to assure that the clear circuit will operate normally: (a) Pull CS Low. (b) The power rising time (tR) must be 10 ms or less. (c) After turning off the power, wait at least 100 ms (tOFF) before attempting to power up the device again. (d) The supply voltage must rise from a voltage lower than 0.1 V. (e) After turning on the power, wait at least 20 ms before attempting to send an instruction to the device.
VCC VCC
0.1 V max
0V tOFF tR 20 ms
(2)
Dummy cycle When the DI input is driven Low, the SK clock cycles preceding a start bit are called "dummy cycles". The device executes dummy cycles when an instruction from the CPU is longer than that for the device. For example, if the CPU's instruction is 16 bits long, the TC9WMC1 executes seven dummy cycles and the TC9WMC2 executes five dummy cycles. Thus, the two instructions take the same number of clock cycles. Erroneous detection of a start bit (a) If the DO output is High during the verify operation, a High on the DI input on the rising edge of SK causes the device to detect erroneously the start of serial reception. To prevent this, the DI input must be driven Low during the verify operation. (b) When the DI and DO pins are configured as a 3-wire interface, data transfer from the CPU and that from the device can collide with each other during a certain period of time and the device cannot detect the start of serial reception correctly. To prevent this, a 10- to 100-K resistor must be inserted between the DI and DO pins, so that the DI input from the CPU takes priority. (See Figure 14.) TC9WMC1 CPU TC9WMC2 SIO DI DO
Figure 13
(3)
Figure 14
(4)
Verify operation (a) The DI input must be driven Low during the verify operation. (b) When the DO output is driven High, a High on the DI input on the rising edge of SK causes the device to detect erroneously the start of serial reception and accepts an instruction. In this case, the DO pin immediately goes to the high-impedance state. Instruction cancellation During an instruction execution, the instruction can be cancelled by pulling the CS pin Low. However, care must be taken for the timing of canceling a write operation as described below. (a) The write operation can be cancelled when the CS is pulled Low on the rising edge of SK when the 15th bit of data is received. (b) The write operation cannot be cancelled when the CS is pulled Low on the rising edge of SK after the 17th bit of data is received. In this case, the write instruction writes the 16 bits of data into the specified memory location.
(5)
10
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TC9WMC1FK/FU,TC9WMC2FK/FU
Absolute Maximum Ratings (Note) (GND = 0 V)
Characteristic Power supply voltage Input voltage Output voltage Power dissipation Storage temperature Operating temperature Symbol VCC VIN VOUT PD Tstg Topr Rating -0.3 to 7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 300 (25C,SM8) 200 (25C,US8) -55 to 125 -40 to 85 Unit V V V mW C C
Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Operating Ranges (Note) (GND = 0 V, Topr = -40 to 85C)
Characteristic Supply voltage (for reading) Supply voltage (for writing) Symbol VCC VCC VIH 1.8 V VCC < 2.7 V 2.7V VCC 3.6 V Low-level input voltage VIL 1.8 V VCC < 2.7 V Operating frequency fsk 2.7V VCC 3.6 V 1.8 V VCC < 2.7 V 0 0 0 Test Condition 2.7V VCC 3.6 V High-level input voltage Min 1.8 2.3 0.7 x VCC 0.8 x VCC 0 Max 3.6 3.6 VCC V VCC 0.3 x VCC 0.2 x VCC 2 0.5 Unit V V
V
MHz
Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND.
Electrical Characteristics DC Characteristics (VCC = 1.8 to 3.6 V, GND = 0 V, Topr = -40 to 85C)
Characteristic Input current Output leakage current High-level output voltage Low-level output voltage Quiescent supply current Supply current during read Supply current during program Symbol ILI ILO VOH VOL ICC1 ICC2 ICC3 fSK = 2 MHz (Note) fSK = 2 MHz IOH = -400 A IOH = -100 A IOL = 2.1 mA IOL = 100 A Test Condition 1.8 VCC < 2.3 V Min VCC - 0.2 Max 1 1 0.2 2 0.5 2.3 VCC < 2.7 V Min VCC - 0.2 Max 1 1 0.2 2 1.0 1.0 2.7 VCC 3.6 V Min VCC - 0.2 Max 1 1 0.2 2 1.5 1.5 Unit A A V V A mA mA
Note: VCC = 1.8 to 2.3 V @fSK = 0.5 MHz
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TC9WMC1FK/FU,TC9WMC2FK/FU
AC Characteristics (VCC = 1.8 to 3.6 V, GND = 0 V, Topr = -40 to 85C)
Characteristic SK clock frequency SK clock pulse width CS Low period CS setup time CS hold time DI setup time DI hold time Propagation delay time (Note) Output disable time Output enable time Symbol fSK tSKH tSKL tCS tCSS tCSH tDS tDH tPD tHZ tSV 1.8 VCC < 2.3 V Min 0 2.0 2.0 0.5 1 0 0.4 0.4 0 0 Max 0.5 2.0 1.0 1.0 2.3 VCC < 2.7 V Min 0 0.5 0.5 0.3 0.4 0 0.2 0.2 0 0 Max 1.5 1.0 0.5 0.5 2.7 VCC 3.6 V Min 0 0.25 0.25 0.2 0.2 0 0.1 0.1 0 0 Max 2 0.4 0.5 0.5 MHz s s s s s s s s s Unit
Note: CL = 100 pF, RL = 1 k
E PROM Characteristics (GND = 0 V, 2.3 V VCC 3.6 V, Topr = -40 to 85C)
Characteristic Program time Rewrite cycle Data retention time Symbol tPW NEW tRET Test Condition 3.0V VCC 3.6 V 2.3V VCC < 3.0 V Min 1 x 10 10
5
2
Max 10 12
Unit ms Times Year
Capacitance Characteristics (Ta = 25C)
Characteristic Input capacitance Output capacitance Symbol CIN CO Test Condition VCC (V) 3.3 3.3 Typ. 4 4 Unit pF pF
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2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
AC Characteristics Timing Chart
tCSS CS tSKH SK tDS DI tPD DO (Read) tSV DO (Verify) tHZ tHZ tPD tDH tDS tDH tSKL tCSH tCS
Input/Output Circuits of Pins
Pin Type Input/Output Circuit Remarks
CS DI SK
Input
Hysteresis input
DO
Output
Initial High Z
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TC9WMC1FK/FU,TC9WMC2FK/FU
Package Dimensions
Weight: 0.01 g (typ.)
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TC9WMC1FK/FU,TC9WMC2FK/FU
Package Dimensions
Weight: 0.02 g (typ.)
15
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TC9WMC1FK/FU,TC9WMC2FK/FU
RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice.
20070701-EN GENERAL
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer's own risk. * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. * Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations.
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2007-10-19

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